1. Field of the Invention
This invention relates to computer system memory subsystems and, more particularly, to memory modules.
2. Description of the Related Art
In many computer systems, one or more processors may be connected to a memory subsystem through a system bus. For example, FIG. 1 illustrates a typical computer system configuration. Computer system 10 includes a plurality of processors 20A–20n connected to a memory subsystem 50 via a system bus 25. Memory subsystem 50 includes a memory controller 30 coupled to a system memory 40 via a memory interconnect 35. It is noted that elements referred to herein with a particular reference number followed by a letter may be collectively referred to by the reference number alone. For example, processor 20A–n may be collectively referred to as processor 20.
Generally speaking, processor 20 may access memory subsystem 50 by initiating a memory request transaction such as a memory read or a memory write to memory controller 30 via system bus 25. Memory controller 30 may then control the storing to and retrieval of data from system memory 40 by issuing memory request commands to system memory 40 via memory interconnect 35. Memory interconnect 35 may convey address and control information and data between system memory 40 and memory controller 30.
Memory subsystem 30 may be configured to store data and instruction code within system memory 40 for use by processor 20. As will be described further below, system memory 40 may be implemented using expandable blocks of memory such as a plurality of dual in-line memory modules (DIMM). Each DIMM may employ a plurality of random access memory chips such as dynamic random access memory (DRAM) or synchronous dynamic random access memory (SDRAM) chips, for example. Each DIMM may be mated to a system memory board via an edge connector and socket arrangement. The socket may be located on a memory subsystem circuit board and each DIMM may have an edge connector which may be inserted into the socket, for example.
The circuit board typically has contact pads or “fingers” arranged on both sides and along one edge of the circuit board. This edge of the circuit board is inserted into a socket having spring-loaded contacts for mating with the fingers. The socket arrangement allows the memory modules to be removed and replaced by a user. In many systems, the memory module connectors are mounted on a motherboard or system board such that the memory modules connect to a memory bus or interconnect one row after another or in a daisy chain. In some cases a computer system may be provided with a given number of memory modules and a user may add modules to expand the system memory capacity.
In many systems, to allow this expandability the memory modules are generally arranged into banks. The banks may be arranged such that each bank may include a particular range of addresses and so when a bank is added, additional memory space is added. In some systems, the banks may be arranged to also allow interleaving of data when it is stored to system memory, thereby possibly improving memory bandwidth.
However in many typical bank arrangements, all the data signals in the data path are routed to each memory module socket. For example, in FIG. 2, a memory subsystem is shown. Memory subsystem 50 includes a memory controller 30 coupled to a system memory including DIMMs 0–3 via a data path having data signals DQ 0–63. It is noted that data signals DQ0–63 are coupled to each DIMM. In the illustrated embodiment, bank 0 corresponds to DIMM 0, bank 1 corresponds to DIMM 1 and so forth. Within each DIMM, DQ 0–15 may correspond to a group of DRAM chips such as DRAM chips 0–4 and DQ 16–31 may correspond to DRAM chips 4–7 and so on. Thus if each data signal path or circuit board trace connected to a memory module socket is a transmission line, then each socket connection point on that transmission line may represent a stub.
Therefore in the illustrated embodiment, each signal in data path DQ0–63 may have as many as four stubs. For systems containing a small number of memory modules, the daisy chain configuration described above may not present any problems. However, in systems with a wide data bus and with many memory modules, a daisy chain configuration may present problems. Each stub in a signal's path may cause undesirable effects such as distortion on signal edges. This type of signal degradation may in turn cause system performance to suffer.